1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to semiconductor devices having V-groove metal oxide semiconductor (VMOS) transistors and VMOS dynamic memory cells. It is most desirable to use the semiconductor devices according to the present invention for a random access memory (RAM).
2. Description of the Prior Art
A VMOS transistor has been produced by anisotropically etching a single-crystalline silicon semiconductor wafer with a (100) plane surface to form a V-groove and then forming a drain, a gate and a source along the slopes of the V-groove (see, for example, Fred B. Jenne: Electronics, Aug. 18, 1977, pp. 100-106).
FIG. 1 is a schematic cross-sectional view of ordinary n-channel VMOS transistors, in which two n-channel VMOS transistors are illustrated. The VMOS transistors are constructed as follows. A substrate 1 is made of a lightly-doped n.sup.- -type silicon single-crystalline wafer. A heavily doped n.sup.+ -type buried layer 2 is formed in the substrate 1 by diffusion or ion implantation. The buried layer 2 serves as a common source of the VMOS transistors. A p-type silicon epitaxial layer 3 is formed on the buried layer 2 and the substrate 1. The surface of the epitaxial layer 3 is the (100) plane. Two V-grooves are formed by anisotropically etching the epitaxial layer 3 as illustrated in FIG. 1. The bottom peaks of the V-grooves reach into the buried layer 2. Around each of the V-grooves a heavily doped n.sup.+ -type region 4 or 5 is formed in a surface portion of the epitaxial layer 3 by ion implantation. The region 4 or 5 serves as a drain of each of the VMOS transistors. A thick silicon dioxide (SiO.sub.2) layer 6 is formed on the epitaxial layer 3 by thermal oxidation. Thin silicon dioxide (SiO.sub.2) layers, i.e., gate oxide layers, 6' and 6" are formed on the surface of the V-grooves by thermal oxidation, respectively. Electron conductive layers, i.e. gate electrodes, 7 and 8 are formed on the thin silicon dioxide layers 6' and 6", respectively. Finally, drain electrodes 9 and 10 are formed in suitable openings of the thick silicon dioxide layer 6 on the drain regions 4 and 5.
A one-transistor memory cell has been provided by combining a VMOS transistor with a buried junction capacitor. FIG. 2 is a schematic cross-sectional view of such one-transistor memory cells, i.e. VMOS dynamic memory cells, in which two one-transistor memory cells are illustrated. The memory cells are constructed as follows. A substrate 11 is made of a p-type silicon single-crystalline wafer. Heavily doped n.sup.+ -type buried layers 12 and 13 are formed in the p-type substrate 11 by diffusion or ion implantation. The reference numerals 3 through 10 indicate parts of the one-transistor memory cells which are the same as those indicated by the reference numerals 3 through 10 of FIG. 1. The bottom peaks of two V-grooves reach into the buried layers 12 and 13, respectively, as illustrated in FIG. 2. Each of the n.sup.+ -type buried layers 12 and 13 serves as a source of a VMOS transistor and a junction capacitor. Since each of the buried layers 12 and 13 has six sides available for storing a charge, the charge capacity of the buried layer is larger than that of a conventional dual-polysilicon type MOS memory cell. The gate electrodes 7 and 8 are connected to word lines (not shown in FIG. 2), respectively, and the drain electrodes 9 and 10 are connected to bit lines (not shown), respectively.
However, the above-mentioned VMOS transistors and one-transistor memory cells (i.e. VMOS dynamic memory cells) can not be formed on the same silicon single-crystalline substrate, since the conductivity type of the substrate used in the VMOS transistors is different from that of the substrate used in the memory cells.